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Members of the Texas Instruments

WidebusE Family

B-Port Outputs Have Equivalent 25-W

Series Resistors, So No External Resistors

Are Required

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

UBT E (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA

Per JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL) Package and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

These 18-bit universal bus transceivers combine

D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and

CLKBA) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the

A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the

latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high,

the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA is active low).

The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-W series resistors

to reduce overshoot and undershoot.