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1 Features

1? Quad 2:1 Mux and 1:2 Demux

? Multi-Rate Operation up to 14.2 Gbps Serial Data

Rate

? Linear Receiver Equalization Which Increases

Margin at System Level of Decision Feedback

Equalizer

? Bandwidth: 18 GHz, Typical

? Per-Lane P/N Pair Inversion

? Port or Single Lane Switching

? Low Power: 150 mW/Channel, Typical

? Loopback Mode on All Three Ports

? I2C Control in Addition to GPIO

? DIAG Mode That Outputs Data of Line Side Port

to Both Fabric Side Ports

? 2.5-V or 3.3-V Single Power Supply

? PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm

Terminal Pitch

? Excellent Impedance Matching to 100-Ω PCB

Transmission Lines

? Small Package Size Provides Board Real Estate

Saving

? Adjustable Output Swing Provides Flexible EMI

and Crosstalk Control

? Low Power

? Supports 10GBASE-KR Applications With Ability

to Transparency for Link Training

2 Applications

? High-Speed Redundancy Switch in Telecom and

Data Communication

? Backplane Interconnect for 10G-KR, 16GFC

3 Description

The SN65LVCP114 device is an asynchronous,

protocol-agnostic, low-latency QUAD mux, linearredriver

optimized for use in systems operating at up

to 14.2 Gbps. The device linearly compensates for

channel loss in backplane and active-cable

applications. The architecture of SN65LVCP114

linear-redriver is designed to work effectively with

ASIC or FPGA products implementing digital

equalization using decision feedback equalizer (DFE)

technology. The SN65LVCP114 mux, linear-redriver

preserves the integrity (composition) of the received

signal, ensuring optimum DFE and system

performance. The SN65LVCP114 provides a lowpower

mux-demux, linear-redriver solution while at

the same time extending the effectiveness of DFE.