国产精品久久久久无码av色戒,大帝av在线一区二区三区,国产肥熟女视频一区二区三区,大陆少妇xxxx做受,被黑人猛躁10次高潮视频

1FEATURES

2? LVDS Interface to Host FPGA

? No External VCO or Clock Ref Required

? Integrated Variable Output Cable Driver

? 3.3V SMBus Configuration Interface

? Integrated TXCLK PLL Cleans Clock Noise

? Small 48-Pin WQFN Package

? Industrial Temperature range: -40°C to 85°C

APPLICATIONS

? SDI Unterfaces for:

– Video Cameras

– DVRs

– Video Switchers

– Video Editing Systems

KEY SPECIFICATIONS

? Output Compliant With SMPTE 424M, SMPTE

292M, SMPTE 259M-C and DVB-ASI (See

Table 1)

? Typical Power Dissipation: 440 mW

? 30 ps Typical Output Jitter (HD, 3G)

DESCRIPTION

The LMH0340/0040/0070/0050 SDI Serializers are

part of TI’s family of FPGA-Attach SER/DES products

supporting 5-bit LVDS interfaces with FPGAs. An

FPGA Host will format data with supplied IP such that

the output of the LMH0340 is compliant with the

requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See Table 1 for

details on which Standards are supported per device.

The interface between the SER (Serializer) and the

FPGA consists of a 5 bit wide LVDS data bus, an

LVDS clock and an SMBus interface. The

LMH0340/0040/0070 SER devices include an

integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The

LMH0050 has a CML output driver that can drive a

differential transmission line or interface to a cable

driver.

The FPGA-Attach SER/DES family is supported by a

suite of IP which allows the design engineer to

quickly develop video applications using the

SER/DES products. The SER is packaged in a

physically small 48-pin WQFN package.