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位置:DS50PCI401SQE/NOPB.A > DS50PCI401SQE/NOPB.A詳情

DS50PCI401SQE/NOPB.A中文資料

廠家型號(hào)

DS50PCI401SQE/NOPB.A

文件大小

656.32Kbytes

頁面數(shù)量

36

功能描述

DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

DS50PCI401SQE/NOPB.A數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

2? Input and Output signal conditioning

increases PCIe reach in backplanes and

cables

? 0.09 UI of residual deterministic jitter at 5Gbps

after 42” of FR4 (with Input EQ)

? 0.11 UI of residual deterministic jitter at 5Gbps interafter

7m of PCIe Cable (with Input EQ)

? 0.09 UI of residual deterministic jitter at 5Gbps

with 28” of FR4 (with Output DE)

? 0.13 UI of residual deterministic jitter at 5Gbps

with 7m of PCIe Cable (with Output DE)

? Adjustable Transmit VOD 800 to 1200mVp-p

? Automatic power management on an

individual lane basis via SMBus

? Adjustable electrical idle detect threshold.

? Data rate optimized 3-stage equalization to 26

dB gain

? Data rate optimized 6-level 0 to 12 dB transmit

de-emphasis

? Flow-thru pinout in 10mmx5.5mm 54-pin

leadless WQFN package

? Single supply operation at 2.5V

? >6kV HBM ESD rating

? -10 to 85°C operating temperature range

DESCRIPTION

The DS50PCI401 is a low power, 4 lane bidirectional

buffer/equalizer designed specifically for PCI Express

Gen1 and Gen2 applications. The device performs

both receive equalization and transmit de-emphasis,

allowing maximum flexibility of physical placement

within a system. The receiver is capable of opening

an input eye that is completely closed due to interafter

symbol interference (ISI) induced by the interconnect

medium.

The transmitter de-emphasis level can be set by the

user depending on the distance from the

DS50PCI401 to the PCI Express endpoint. The DS50PCI401 contains PCI Express specific functions

such as Transmit Idle, RX Detection, and Beacon

signal pass through.

The device will change the load impedance on its

input pins based on the state of RXDETA/B inputs

detection. An internal rate detection circuit is included

to detect if an incoming data stream is at Gen2 data

rates, and adjusts the de-emphasis on it's output

accordingly. The signal conditioning provided by the

device allows systems to upgrade from Gen1 data

rates to Gen2 without reducing their physical reach.

This is true for FR4 applications such as backplanes,

as well as cable interconnect.

更新時(shí)間:2025-9-21 14:01:00
供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
NSC
24+
QFN52
6980
原裝現(xiàn)貨,可開13%稅票
NS
23+
QFN
6500
專注配單,只做原裝進(jìn)口現(xiàn)貨
NS
24+
QFN
19000
只做正品原裝現(xiàn)貨
TI德州儀器
22+
24000
原裝正品現(xiàn)貨,實(shí)單可談,量大價(jià)優(yōu)
24+
N/A
58000
一級(jí)代理-主營優(yōu)勢(shì)-實(shí)惠價(jià)格-不悔選擇
TI
2016+
WQFN54
3000
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TI
1706+
WQFN54
9100
只做原裝進(jìn)口,假一罰十
TI/德州儀器
24+
WQFN54
2000
訂貨中主營TI
TI
20+
NA
53650
TI原裝主營-可開原型號(hào)增稅票
TI
20+
WQFN54
11520
特價(jià)全新原裝公司現(xiàn)貨