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位置:DS34C86TMX/NOPB.A > DS34C86TMX/NOPB.A詳情

DS34C86TMX/NOPB.A中文資料

廠家型號(hào)

DS34C86TMX/NOPB.A

文件大小

397.82Kbytes

頁(yè)面數(shù)量

13頁(yè)

功能描述

DS34C86T Quad CMOS Differential Line Receiver

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

DS34C86TMX/NOPB.A數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

1FEATURES

2? CMOS Design for Low Power

? ±0.2V Sensitivity Over the Input Common

Mode Voltage Range

? Typical Propagation Delays: 19 ns

? Typical Input Hysteresis: 60 mV

? Inputs Won't Load Line when VCC = 0V

? Meets the Requirements of EIA Standard RS-

422

? TRI-STATE Outputs for System Bus

Compatibility

? Available in Surface Mount

? Open Input Failsafe Feature, Output High for

Open Input

DESCRIPTION

The DS34C86T is a quad differential line receiver

designed to meet the RS-422, RS-423, and Federal

Standards 1020 and 1030 for balanced and

unbalanced digital data transmission, while retaining

the low power characteristics of CMOS.

The DS34C86T has an input sensitivity of 200 mV

over the common mode input voltage range of ±7V.

Hysteresis is provided to improve noise margin and

discourage output instability for slowly changing input

waveforms.

The DS34C86T features internal pull-up and pulldown

resistors which prevent output oscillation on

unused channels.

Separate enable pins allow independent control of

receiver pairs. The TRI-STATE outputs have 6 mA

source and sink capability. The DS34C86T is pin

compatible with the DS3486.

更新時(shí)間:2025-8-19 13:30:00
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