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位置:DS26C32ATMSLASHNOPB.A > DS26C32ATMSLASHNOPB.A詳情

DS26C32ATMSLASHNOPB.A中文資料

廠家型號(hào)

DS26C32ATMSLASHNOPB.A

文件大小

517.299Kbytes

頁(yè)面數(shù)量

16頁(yè)

功能描述

DS26C32AT/DS26C32AM Quad Differential Line Receiver

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

DS26C32ATMSLASHNOPB.A數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

1FEATURES

2? CMOS Design for Low Power

? ±0.2V Sensitivity over Input Common Mode

Voltage Range

? Typical Propagation Delays: 19 ns

? Typical Input hysteresis: 60 mV

? Inputs Won't Load Line When VCC = 0V

? Meets the Requirements of EIA Standard RS-422

? TRI-STATE Outputs for Connection to System

Buses

? Available in Surface Mount

? Mil-Std-883C Compliant

DESCRIPTION

The DS26C32A is a quad differential line receiver

designed to meet the RS-422, RS-423, and Federal

Standards 1020 and 1030 for balanced and

unbalanced digital data transmission, while retaining

the low power characteristics of CMOS.

The DS26C32A has an input sensitivity of 200 mV

over the common mode input voltage range of ±7V.

The DS26C32A features internal pull-up and pull

down resistors which prevent output oscillation on

unused channels.

The DS26C32A provides an enable and disable

function common to all four receivers. It also features

TRI-STATE outputs with 6 mA source and sink

capability. This product is pin compatible with the

DS26LS32A and the AM26LS32.

更新時(shí)間:2025-9-10 11:03:00
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