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位置:DAC102S085CISDSLASHNO.A > DAC102S085CISDSLASHNO.A詳情

DAC102S085CISDSLASHNO.A中文資料

廠家型號(hào)

DAC102S085CISDSLASHNO.A

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1101.54Kbytes

頁(yè)面數(shù)量

34頁(yè)

功能描述

DAC102S085 10-Bit Micro Power DUAL Digital-to-Analog Converter With Rail-to-Rail Output

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

DAC102S085CISDSLASHNO.A數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

1 Features

1? Ensured Monotonicity

? Low Power Operation

? Rail-to-Rail Voltage Output

? Power-On Reset to 0 V

? Simultaneous Output Updating

? Wide Power Supply Range (2.7 V to 5.5 V)

? Industry's Smallest Package

? Power Down Modes

? Key Specifications

– Resolution: 10 Bits

– INL: ±2 LSB (Maximum)

– DNL: +0.35 or –0.25 LSB (Maximum)

– Settling Time: 6 μs (Maximum)

– Zero Code Error: 15 mV (Maximum)

– Full-Scale Error: –0.75% FS (Maximum)

– Supply Power

– Normal: 0.6 mW at 3 V, 1.6 mW at 5 V

(Typical)

– Power Down: 0.3 μW at 3 V, 0.8 μW at 5 V

(Typical)

2 Applications

? Battery-Powered Instruments

? Digital Gain and Offset Adjustment

? Programmable Voltage and Current Sources

? Programmable Attenuators

3 Description

The DAC102S085 is a full-featured, general-purpose

DUAL 10-bit voltage-output digital-to-analog converter

(DAC) that can operate from a single 2.7-V to 5.5-V

supply and consumes 0.6 mW at 3 V and 1.6 mW at

5 V. The DAC102S085 is packaged in 10-pin WSON

and VSSOP packages. The 10-pin WSON package

makes the DAC102S085 the smallest DUAL DAC in

its class. The on-chip output amplifier allows rail-torail

output swing and the three wire serial interface

operates at clock rates up to 40 MHz over the entire

supply voltage range. Competitive devices are limited

to 25-MHz clock rates at supply voltages in the 2.7-V

to 3.6-V range. The serial interface is compatible with

standard SPI?, QSPI, MICROWIRE and DSP

interfaces.

The reference for the DAC102S085 serves both

channels and can vary in voltage between 1 V and

VA, providing the widest possible output dynamic

range. The DAC102S085 has a 16-bit input shift

register that controls the outputs to be updated, the

mode of operation, the power-down condition, and

the binary input data. Both outputs can be updated

simultaneously or individually depending on the

setting of the two mode of operation bits.

更新時(shí)間:2025-9-22 13:33:00
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全新、原裝