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DAC084S085CISDSLASHNO.A中文資料

廠家型號(hào)

DAC084S085CISDSLASHNO.A

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1067.03Kbytes

頁(yè)面數(shù)量

35頁(yè)

功能描述

DAC084S085 8-Bit Micropower QUAD Digital-to-Analog Converter With Rail-to-Rail Output

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

DAC084S085CISDSLASHNO.A數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

1 Features

1? Ensured Monotonicity

? Low-Power Operation

? Rail-to-Rail Voltage Output

? Power-On Reset to 0 V

? Simultaneous Output Updating

? Wide Power Supply Range (2.7 V to 5.5 V)

? Industry's Smallest Package

? Power Down Modes

? Key Specifications

– Resolution: 8 Bits

– INL: ±0.5 LSB (Maximum)

– DNL: +0.18 / ?0.13 LSB (Maximum)

– Setting Time: 4.5 μs (Maximum)

– Zero Code Error: +15 mV (Maximum)

– Full-Scale Error: ?0.75 %FS (Maximum)

– Supply Power:

– Normal: 1.1 mW (3 V) / 2.5 mW (5 V)

Typical

– Power Down: 0.3 μW (3 V) / 0.8 μW (5 V)

Typical

2 Applications

? Battery-Powered Instruments

? Digital Gain and Offset Adjustment

? Programmable Voltage and Current Sources

? Programmable Attenuators

3 Description

The DAC084S085 is a full-featured, general-purpose

QUAD 8-bit voltage-output digital-to-analog converter

(DAC) that can operate from a single 2.7-V to 5.5-V

supply and consumes 1.1 mW at 3 V and 2.5 mW at

5 V. The DAC084S085 is packaged in 10-pin SON

and VSSOP packages. The 10-pin SON package

makes the DAC084S085 the smallest QUAD DAC in

its class. The on-chip output amplifier allows rail-torail

output swing and the three wire serial interface

operates at clock rates up to 40 MHz over the entire

supply voltage range. Competitive devices are limited

to 25-MHz clock rates at supply voltages in the 2.7-V

to 3.6-V range. The serial interface is compatible with

standard SPI, QSPI, MICROWIRE, and DSP

interfaces.

The reference for the DAC084S085 serves all four

channels and can vary in voltage between 1 V and

VA, providing the widest possible output dynamic

range. The DAC084S085 has a 16-bit input shift

register that controls the outputs to be updated, the

mode of operation, the power-down condition, and

the binary input data. All four outputs can be updated

simultaneously or individually depending on the

setting of the two mode of operation bits.

更新時(shí)間:2025-9-22 8:01:00
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