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位置:CD74HC4046APW.A > CD74HC4046APW.A詳情

CD74HC4046APW.A中文資料

廠家型號(hào)

CD74HC4046APW.A

文件大小

830.74Kbytes

頁(yè)面數(shù)量

37頁(yè)

功能描述

High-Speed CMOS Logic Phase-Locked Loop with VCO

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

CD74HC4046APW.A數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

Features

? Operating Frequency Range

- Up to 18MHz (Typ) at VCC = 5V

- Minimum Center Frequency of 12MHz at VCC = 4.5V

? Choice of Three Phase Comparators

- EXCLUSIVE-OR

- Edge-Triggered JK Flip-Flop

- Edge-Triggered RS Flip-Flop

? Excellent VCO Frequency Linearity

? VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

? Minimal Frequency Drift

? Operating Power Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

? Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

? Wide Operating Temperature Range . . . -55oC to 125oC

? Balanced Propagation Delay and Transition Times

? Significant Power Reduction Compared to LSTTL

Logic ICs

? HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

? HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Applications

? FM Modulation and Demodulation

? Frequency Synthesis and Multiplication

? Frequency Discrimination

? Tone Decoding

? Data Synchronization and Conditioning

? Voltage-to-Frequency Conversion

? Motor-Speed Control

Description

The ’HC4046A and ’HCT4046A are high-speed silicon-gate

CMOS devices that are pin compatible with the CD4046B of

the “4000B” series. They are specified in compliance with

JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop

circuits that contain a linear voltage-controlled oscillator

(VCO) and three different phase comparators (PC1, PC2 and

PC3). A signal input and a comparator input are common to

each comparator.

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage

signals within the linear region of the input amplifiers. With a

passive low-pass filter, the 4046A forms a second-order loop

PLL. The excellent VCO linearity is achieved by the use of

linear op-amp techniques.

更新時(shí)間:2025-9-23 14:30:00
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