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1FEATURES

2? Internal Sample-and-Hold

? Single +1.9V ±0.1V Operation

? Adjustable Output Levels

? Ensured No Missing Codes

? Low Power Standby Mode

APPLICATIONS

? Direct RF Down Conversion self?

Digital Oscilloscopes

? Satellite Set-top boxes

? Communications Systems

? Test Instrumentation

APPLICATIONS

? Resolution 8 Bits

? Max Conversion Rate 1 GSPS (Min)

? ENOB at 500 MHz Input 7.5 Bits (Typ)

? DNL ±0.25 LSB (Typ)

? Conversion Latency 7 and 8 Clock Cycles

? Power Consumption

– Operating 1.45 W (Typ)

– Power Down Mode 9 mW (Typ)

DESCRIPTION

The ADC081000 is a low power, high performance

CMOS analog-to-digital converter that digitizes

signals to 8 bits resolution at sampling rates up to

1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS

from a single 1.9 Volt supply, this device is ensured

to have no missing codes over the full operating temperature range. The unique folding and

interpolating architecture, the fully differential

comparator design, the innovative design of the

internal sample-and-hold amplifier and the self?

calibration scheme enable a very flat response of all

dynamic parameters beyond Nyquist, producing a

high 7.5 ENOB with a 500 MHz input signal and a

1 GHz sample rate while providing a 10-18 B.E.R.

Output formatting is offset binary and the LVDS

digital outputs are compliant with IEEE 1596.3-1996,

with the exception of a reduced common mode voltage of 0.8V.

The converter has a 1:2 demultiplexer that feeds two

LVDS buses, reducing the output data rate on each

bus to half the sampling rate. The data on these

buses are interleaved in time to provide a 500 MHz

output rate per bus and a combined output rate of

1 GSPS.

The converter typically consumes less than 10 mW in

the Power Down Mode and is available in a 128-lead

HLQFP and operates over the industrial (–40°C ≤

TA ≤ +85°C) temperature range.