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位置:74ALVCH16841DGGRG4.B > 74ALVCH16841DGGRG4.B詳情

74ALVCH16841DGGRG4.B中文資料

廠家型號(hào)

74ALVCH16841DGGRG4.B

文件大小

589.24Kbytes

頁(yè)面數(shù)量

19頁(yè)

功能描述

20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

74ALVCH16841DGGRG4.B數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 20-bit bus-interface D-type latch is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH16841 features 3-state outputs

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer registers,

unidirectional bus drivers, and working registers.

The SN74ALVCH16841 can be used as two 10-bit

latches or one 20-bit latch. The 20 latches are

transparent D-type latches. The device has

noninverting data (D) inputs and provides true data at

its outputs. While the latch-enable (1LE or 2LE) input

is high, the Q outputs of the corresponding 10-bit

latch follow the D inputs. When LE is taken low, the Q

outputs are latched at the levels set up at the D

inputs.

A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch

in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,

the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16841 is characterized for operation from -40°C to 85°C.

更新時(shí)間:2025-9-20 13:48:00
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MICROCHIP/微芯
23+
SOT23-5
69820
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Nexperia USA Inc.
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56-TSSOP
56200
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100500
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NEXPERIA
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SSOP-56
4854
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Nexperia(安世)
2021+
TSSOP-56
499
恩XP
2021+
DHVQFN-20
7600
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恩XP
24+
DHVQFN-20
30000
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恩XP
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DHVQFN-20
8080
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25+
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8880
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恩XP
23+
DHVQFN-20
8080
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