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DESCRIPTION

These devices are high-speed Hex Buffers with 3-

state outputs. They are organized as single 6-bit or

2-bit/4-bit, with inverting or non-inverting data (D)

paths. The outputs are designed to drive 15 TTL Unit

Loads or 60 Low Power Schottky loads when the

Enable (E) is LOW.

When the output Enable input (E) is HIGH, the out-

puts are forced to a high impedance off state. If the

outputs of the 3-state devices are tied together, all

but one device must be in the high impedence state

to avoid high currents that woud exceed the maxi-

mum ratings. Designers should ensure that Output

Enable signals to 3-state devices, whose outputs

are tied together, are designed so there is no over-

lap.