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位置:PM7364 > PM7364詳情

PM7364中文資料

廠家型號

PM7364

文件大小

39.74Kbytes

頁面數(shù)量

2

功能描述

Frame Engine and Datalink Manager

FRAME ENGINE AND DATA LINK MANAGER

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

簡稱

PMC

生產(chǎn)廠商

PMC-Sierra, Inc

中文名稱

官網(wǎng)

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PM7364數(shù)據(jù)手冊規(guī)格書PDF詳情

DESCRIPTION

The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels.

FEATURES

? Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.

? Supports up to 128 bi-directional HDLC channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1).

? Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can have a clock rate of up to 10 MHz.

? Supports up to two bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz.

? Supports a mix of up to 32 channelised and unchannelised links; subject to the constraint of a maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each direction.

? For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.

? Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.

? For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.

? For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.

? Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.

? Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.

? Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities.

? Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 128 channels, each with a minimum of 48 bytes of buffering.

? Supports PCI burst sizes of up to 128 bytes for transfers of packet data.

? Pin compatible with PM7366 (FREEDM-8) device.

? Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

? Supports 3.3 and 5 Volt PCI signaling environments.

? Low power CMOS technology.

? 256 pin enhanced ball grid array (SBGA) package (27 mm X 27 mm).

APPLICATIONS

? IETF PPP interfaces for routers

? Frame Relay interfaces for ATM or Frame Relay switches and multiplexors

? FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.

? D-channel processing in ISDN terminals and switches.

? Internet/Intranet access equipment.

? Packet-based DSLAM equipment.

PM7364產(chǎn)品屬性

  • 類型

    描述

  • 型號

    PM7364

  • 制造商

    PMC

  • 制造商全稱

    PMC

  • 功能描述

    FRAME ENGINE AND DATA LINK MANAGER

更新時間:2025-7-10 16:36:00
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PMC-Sierra, Inc

中文資料: 539條

PMC-Sierra, Inc. 是一家專注于網(wǎng)絡(luò)和存儲半導(dǎo)體解決方案的公司,成立于1986年,總部位于美國加利福尼亞州。該公司致力于為數(shù)據(jù)中心、企業(yè)網(wǎng)絡(luò)和電信市場提供高性能的集成電路和相關(guān)技術(shù)。PMC-Sierra 的產(chǎn)品線包括網(wǎng)絡(luò)處理器、存儲控制器和光纖通道解決方案,廣泛應(yīng)用于服務(wù)器、路由器和交換機(jī)等設(shè)備中。憑借其在技術(shù)創(chuàng)新和設(shè)計(jì)方面的領(lǐng)先地位,PMC-Sierra 致力于幫助客戶提高數(shù)據(jù)傳輸速度和系統(tǒng)性能。2016年,公司被 Broadcom Inc. 收購,進(jìn)一步增強(qiáng)了其在半導(dǎo)體行業(yè)的競爭力。