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DESCRIPTION

The 74F50729 is a dual positive edge–triggered D–type featuring individual data, clock, set and reset inputs; also true and complementary outputs.

The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: τ ? 135ps and τ ? 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.

FEATURES

? Metastable immune characteristics

? Output skew less than 1.5ns

? High source current (IOH = 15mA) ideal for clock driver applications

? See 74F5074 for synchronizing dual D–type flip–flop

? See 74F50109 for synchronizing dual J–K positive edge–triggered flip–flop

? See 74F50728 for synchronizing cascaded dual D–type flip–flop

? Industrial temperature range available (–40°C to +85°C)