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位置：74ALVT16841DGG > 74ALVT16841DGG詳情

74ALVT16841DGG中文資料

廠家型號

74ALVT16841DGG
文件大小

96.17Kbytes
頁面數(shù)量

14頁
功能描述

2.5V/3.3V ALVT 20-bit bus interface latch 3-State
數(shù)據(jù)手冊

下載地址一下載地址二
生產(chǎn)廠商

PHI

74ALVT16841DGG數(shù)據(jù)手冊規(guī)格書PDF詳情

DESCRIPTION

The 74ALVT16841 Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V.

FEATURES

? High speed parallel latches

? 5V I/O Compatible

? Live insertion/extraction permitted

? Extra data width for wide address/data paths or buses carrying parity

? Power-up 3-State

? Power-up reset

? Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors

? Output capability: +64mA/–32mA

? Latch-up protection exceeds 500mA per Jedec Std 17

? Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

? ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

更新時間：2025-9-7 11:02:00
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