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位置：74ALS373DB > 74ALS373DB詳情

74ALS373DB中文資料

廠家型號(hào)

74ALS373DB
文件大小

144.77Kbytes
頁(yè)面數(shù)量

13頁(yè)
功能描述

Latch/flip-flop
數(shù)據(jù)手冊(cè)

下載地址一下載地址二
生產(chǎn)廠商

PHI

74ALS373DB數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

DESCRIPTION

The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.

The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

FEATURES

? 8-bit transparent latch – 74ALS373

? 8-bit positive edge triggered register – 74ALS374

? 3-State output buffers

? Common 3-State output register

? Independent register and 3-State buffer operation

更新時(shí)間：2025-9-17 16:06:00
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