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位置：74AHCT132PWDH > 74AHCT132PWDH詳情

74AHCT132PWDH中文資料

廠家型號(hào)

74AHCT132PWDH
文件大小

106.13Kbytes
頁(yè)面數(shù)量

16頁(yè)
功能描述

Quad 2-input NAND Schmitt trigger
數(shù)據(jù)手冊(cè)

下載地址一下載地址二
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74AHCT132PWDH數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

DESCRIPTION

The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter free output signals.

The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative VT? is defined as the hysteresis voltage VH.

FEATURES

? ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V;

MM EIA/JESD22-A115-A

exceeds 200 V

CDM EIA/JESD22-C101

exceeds 1000 V

? Balanced propagation delays

? Inputs accepts voltages higher than VCC

? For AHC only:

operates with CMOS input levels

? For AHCT only:

operates with TTL input levels

? Specified from

?40 to +85 and +125 °C.

更新時(shí)間：2025-9-18 16:17:00
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