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Description

The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that

uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page

family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C

have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of

a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on

whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or

x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate

to other densities without changing the footprint.

To extend the lifetime of NAND Flash devices it is strongly recommended to implement an

Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000

program/erase cycles for each block. A Write Protect pin is available to give a hardware

protection against program and erase operations.

Features

● High density NAND Flash memories

– 512 Mbit memory array

– Cost effective solutions for mass storage applications

● NAND interface

– x 8 or x 16 bus width

– Multiplexed Address/ Data

● Supply voltage: 1.8 V, 3.0 V

● Page size

– x 8 device: (512 + 16 spare) bytes

– x 16 device: (256 + 8 spare) words

● Block size

– x 8 device: (16 K + 512 spare) bytes

– x 16 device: (8 K + 256 spare) words

● Page Read/Program

– Random access: 12 μs (3 V)/15 μs (1.8 V) (max)

– Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)

– Page Program time: 200 μs (typ)

● Copy Back Program mode

● Fast Block Erase: 2 ms (typ)

● Status Register

● Electronic signature

● Chip Enable ‘don’t care’

● Serial Number option

● Hardware Data Protection

– Program/Erase locked during Power transitions

● Data integrity

– 100,000 Program/Erase cycles (with ECC)

– 10 years Data Retention

● ECOPACK? packages

● Development tools

– Error Correction Code models

– Bad Blocks Management and Wear Leveling algorithms

– Hardware simulation models