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DEVICE OVERVIEW

This document contains device-specific information for the following devices:

? PIC24FJ64GB106 ? PIC24FJ192GB108

? PIC24FJ128GB106 ? PIC24FJ256GB108

? PIC24FJ192GB106 ? PIC24FJ64GB110

? PIC24FJ256GB106 ? PIC24FJ128GB110

? PIC24FJ64GB108 ? PIC24FJ192GB110

? PIC24FJ128GB108 ? PIC24FJ256GB110

This expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 family provides a new platform for high-performance USB applications, which may need more than an 8-bit platform, but don’t require the power of a digital signal processor.

Power Management:

? On-Chip 2.5V Voltage Regulator

? Switch between Clock Sources in Real Time

? Idle, Sleep and Doze modes with Fast Wake-up and

Two-Speed Start-up

? Run mode: 1 mA/MIPS, 2.0V Typical

? Sleep mode Current Down to 100 nA Typical

? Standby Current with 32 kHz Oscillator: 2.5 ?A,

2.0V typical

Universal Serial Bus Features:

? USB v2.0 On-The-Go (OTG) Compliant

? Dual Role Capable – can act as either Host or Peripheral

? Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB

Operation in Host mode

? Full-Speed USB Operation in Device mode

? High-Precision PLL for USB

? Internal Voltage Boost Assist for USB Bus Voltage

Generation

? Interface for Off-Chip Charge Pump for USB Bus

Voltage Generation

? Supports up to 32 Endpoints (16 bidirectional):

- USB Module can use any RAM location on the

device as USB endpoint buffers

? On-Chip USB Transceiver with On-Chip Voltage Regulator

? Interface for Off-Chip USB Transceiver

? Supports Control, Interrupt, Isochronous and Bulk Transfers

? On-Chip Pull-up and Pull-Down Resistors

High-Performance CPU:

? Modified Harvard Architecture

? Up to 16 MIPS Operation at 32 MHz

? 8 MHz Internal Oscillator

? 17-Bit x 17-Bit Single-Cycle Hardware Multiplier

? 32-Bit by 16-Bit Hardware Divider

? 16 x 16-Bit Working Register Array

? C Compiler Optimized Instruction Set Architecture with

Flexible Addressing modes

? Linear Program Memory Addressing, Up to 12 Mbytes

? Linear Data Memory Addressing, Up to 64 Kbytes

? Two Address Generation Units for Separate Read and

Write Addressing of Data Memory

Analog Features:

? 10-Bit, Up to 16-Channel Analog-to-Digital (A/D)

Converter at 500 ksps:

- Conversions available in Sleep mode

? Three Analog Comparators with Programmable Input/

Output Configuration

? Charge Time Measurement Unit (CTMU) (Continue ...)