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Extreme Low-Power Features

? Multiple Power Management Options for Extreme Power

Reduction:

- VBAT allows for lowest power consumption on backup

battery (with or without RTCC)

- Deep Sleep allows near total power-down with the ability to

wake-up on external triggers

- Sleep and Idle modes selectively shut down peripherals

and/or core for substantial power reduction and fast wake-up

- Doze mode allows CPU to run at a lower clock speed than

peripherals

? Alternate Clock modes allow On-the-Fly Switching to a Lower

Clock Speed for Selective Power Reduction

? Extreme Low-Power Current Consumption for Deep Sleep:

- WDT: 650 nA @ 2V typical

- RTCC: 650 nA @ 32 kHz, 2V typical

- Deep Sleep current, 60 nA typical

? 160 ?A/MHz in Run mode

High-Performance CPU

? Modified Harvard Architecture

? Up to 16 MIPS Operation @ 32 MHz

? 8 MHz Internal Oscillator:

- 96 MHz PLL option

- Multiple clock divide options

- Run-time self-calibration capability for maintaining better

than ±0.20% accuracy

- Fast start-up

? 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier

? 32-Bit by 16-Bit Hardware Divider

? 16 x 16-Bit Working Register Array

? C Compiler Optimized Instruction Set Architecture

? Two Address Generation Units for Separate Read and Write

Addressing of Data Memory

Cryptographic Engine

? Performs NIST Standard Encryption/Decryption

Operations without CPU Intervention

? AES Cipher Support for 128, 192 and 256-Bit Keys

? DES/3DES Cipher Support, with up to Three Unique Keys

for 3DES

? Supports ECB, CBC, OFB, CTR and CFB128 modes

? Programmatically Secure OTP Array for Key Storage

? True Random Number Generation

? Battery-Backed RAM Key Storage

Analog Features

? 10/12-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter:

- Conversion rate of 500 ksps (10-bit), 200 kbps (12-bit)

- Auto-scan and threshold compare features

- Conversion available during Sleep

? One 10-Bit Digital-to-Analog Converter (DAC):

- 1 Msps update rate

? Three Rail-to-Rail, Enhanced Analog Comparators with

Programmable Input/Output Configuration

? Charge Time Measurement Unit (CTMU):

- Used for capacitive touch sensing, up to 24 channels

- Time measurement down to 100 ps resolution

Dual Partition Flash with Live Update

Capability

? Capable of Holding Two Independent Software Applications,

including Bootloader

? Permits Simultaneous Programming of One Partition while

Executing Application Code from the Other

? Allows Run-Time Switching Between Active Partitions

Universal Serial Bus Features

(PIC24FJXXXGB4XX Only)

? USB v2.0 On-The-Go (OTG) Compliant

? Dual Role Capable – Can Act as Either Host or Peripheral

? Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB

Operation in Host mode

? Full-Speed USB Operation in Device mode

? High-Precision PLL for USB

? USB Device mode Operation from FRC Oscillator – No Crystal

Oscillator Required

? Supports up to 32 Endpoints (16 bidirectional):

- USB module can use any RAM locations on the device as

USB endpoint buffers

? On-Chip USB Transceiver with Interface for Off-Chip

USB Transceiver

? Supports Control, Interrupt, Isochronous and Bulk Transfers

? On-Chip Pull-up and Pull-Down Resistors

Special Microcontroller Features

? 20,000 Erase/Write Cycle Endurance, Typical

? Data Retention: 20 Years Minimum

? Self-Programmable under Software Control

? Supply Voltage Range of 2.0V to 3.6V

? Two On-Chip Voltage Regulators (1.8V and 1.2V) for

Regular and Extreme Low-Power Operation

? Programmable Reference Clock Output

? In-Circuit Serial Programming? (ICSP?) and

In-Circuit Emulation (ICE) via 2 Pins

? JTAG Boundary Scan Support

? Fail-Safe Clock Monitor (FSCM) Operation:

- Detects clock failure and switches to on-chip,

Low-Power RC (LPRC) Oscillator

? Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

? Separate Brown-out Reset (BOR) and Deep Sleep

Brown-out Reset (DSBOR) Circuits

? Programmable High/Low-Voltage Detect (HLVD)

? Flexible Watchdog Timer (WDT) with its Own

RC Oscillator for Reliable Operation

? Standard and Ultra Low-Power Watchdog Timers (ULPW) for

Reliable Operation in Standard and Deep Sleep modes

? Temperature Range: -40°C to +85°C

Peripheral Features

? LCD Display Controller:

- Up to 64 Segments by 8 Commons

- Internal charge pump and low-power, internal resistor biasing

- Operation in Sleep mode

? Up to Five External Interrupt Sources

? Peripheral Pin Select (PPS); allows Independent

I/O Mapping of Many Peripherals

? Six-Channel DMA Supports All Peripheral modules:

- Minimizes CPU overhead and increases

data throughput

? Five 16-Bit Timers/Counters with Prescalers:

- Can be paired as 32-bit timers/counters

? Using a combination of Timer, CCP, IC and OC Timers, the

Device can be Configured to use up to 31 16-Bit Timers,

and up to 15 32-Bit Timers

? Six Input Capture modules, each with a Dedicated

16-Bit Timer

? Six Output Compare/PWM modules, each with a

Dedicated 16-Bit Timer

? Six Single Output CCPs (SCCP) and One Multiple

Output CCP (MCCP) modules:

- Independent 16/32-bit time base for each module

- Internal time base and Period registers

- Legacy PIC24F Capture and Compare modes

(16 and 32-bit)

- Special variable frequency pulse and Brushless DC Motor

(BDCM) Output modes

? Enhanced Parallel Master/Slave Port (EPMP/EPSP)

? Hardware Real-Time Clock/Calendar (RTCC) with

Timestamping:

- Tamper detection with timestamping feature and

tamper pin

- Runs in Deep Sleep and VBAT modes

? Four Three-Wire/Four-Wire SPI modules (support four Frame

modes) with 8-Level FIFO Buffer

? Three I2C modules support Multi-Master/Slave mode and

7-Bit/10-Bit Addressing

? Six UART modules:

- Support RS-485, RS-232 and LIN/J2602

- On-chip hardware encoder/decoder for IrDA?

- Auto-wake-up on Auto-Baud Detect (ABD)

- Four-level deep FIFO buffer

? Programmable 32-Bit Cyclic Redundancy Check (CRC)

Generator

? Four Configurable Logic Cells (CLCs):

- Two inputs and one output, all mappable to

peripherals or I/O pins

- AND/OR/XOR logic and D/JK flip-flop functions

? High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

? Configurable Open-Drain Outputs on Digital I/O Pins

? 5.5V Tolerant Inputs on Multiple I/O Pins