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ARCHITECTURAL OVERVIEW

The PCI-EISA bridge chip set provides an I/O subsystem core for the next generation of high-performance personal computers (e.g., those based on the Intel486TM or Pentiumé processors). System designers can take advantage of the power of the PCI local bus while maintaining access to the large base of EISA and ISA expansion cards, and corresponding software applications. Extensive buffering and buffer management within the PCI-EISA bridge ensures maximum efficiency in both bus environments.

■ Provides the Bridge Between the PCI Local Bus and EISA Bus

■ 100 PCI and EISA Compatible

— PCI and EISA Master/Slave Interface

— Directly Drives 10 PCI Loads and 8 EISA Slots

— Supports PCI from 25 to 33 MHz

■ Data Buffers Improve Performance

— Four 32-bit PCI-to-EISA Posted Write Buffers

— Four 16-byte EISA-to-PCI Read/Write Line Buffers

— EISA-to-PCI Read Prefetch

— EISA-to-PCI and PCI-to-EISA Write Posting

■ Data Buffer Management Ensures Data Coherency

— Flush Posted Write Buffers

— Flush or Invalidate Line Buffers

— System-Wide Data Buffer Coherency Control

■ Burst Transfers on both the PCI and EISA Buses

■ 32-Bit Data Paths

■ Integrated EISA Data Swap Buffers

■ Arbitration for PCI Devices

— Supports Six PCI Masters

— Fixed, Rotating, or a Combination of the Two

— Supports External PCI Arbiter and Arbiter Cascading

■ PCI and EISA Address Decoding and Mapping

— Positive Decode of Main Memory Areas (MEMCSY Generation)

— Four Programmable PCI Memory Space Regions

— Four Programmable PCI I/O Space Regions

■ Programmable Main Memory Address Decoding

— Main Memory Sizes up to 512 MBytes

— Access Attributes for 15 Memory Segments in First 1 MByte of Main Memory

— Programmable Main Memory Hole

■ Integrated 16-bit BIOS Timer

■ Only Available as Part of a Supported Kit