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PRODUCT OVERVIEW

The 28F008SA-L is a high-performance 8-Mbit (8,388,608-bit) memory organized as 1 Mbyte (1,048,576 bytes) of 8 bits each. Sixteen 64-Kbyte (65,536-byte) blocks are included on the 28F008SA-L. A memory map is shown in Figure 6 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 2.0 seconds, independent of the remaining blocks. Each block can be independently erased and written 10,000 cycles. Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the 28F008SA-L.

■ High-Density Symmetrically-Blocked Architecture

— Sixteen 64-Kbyte Blocks

■ Low-Voltage Operation

— -3.3V g0.3V or 5.0V ±10 VCC

■ Extended Cycling Capability

— 10,000 Block Erase Cycles

— 160,000 Block Erase Cycles per Chip

■ Automated Byte Write and Block Erase

— Command User Interface

— Status Register

■ System Performance Enhancements

— RY/BYY # Status Output

— Erase Suspend Capability

■ High-Performance Read

— 200 ns Maximum Access Time

■ Deep Power-Down Mode

— 0.20 μA ICC Typical

■ SRAM-Compatible Write Interface

■ Hardware Data Protection Feature

— Erase/Write Lockout during Power Transitions

■ Industry Standard Packaging

— 40-Lead TSOP, 44-Lead PSOP

■ ETOX? III Nonvolatile Flash Technology

— 12V Byte Write/Block Erase