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Description

Atmels AT91SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32-bit ARM7? RISC processor and high-speed Flash memory.

? AT91SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM.

? AT91SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM.

? AT91SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM.

It also embeds a large set of peripherals, including a USB 2.0 device, an External Bus Interface (EBI), and a complete set of system functions minimizing the number of external components.

The EBI incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific circuitry facilitating the interface for NAND Flash, SmartMedia and CompactFlash.

Features

? Incorporates the ARM7TDMI? ARM? Thumb? Processor

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE? In-circuit Emulation, Debug Communication Channel Support

? Internal High-speed Flash

– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual Plane (AT91SAM7SE512)

– 256 Kbytes (AT91SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes Single Plane (AT91SAM7SE256)

– 32 Kbytes (AT91SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes Single Plane (AT91SAM7SE32)

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms

– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit

– Fast Flash Programming Interface for High Volume Production

? 32 Kbytes (AT91SAM7SE512/256) or 8 Kbytes (AT91SAM7SE32) of Internal High-speed SRAM, Single-cycle Access at Maximum Speed

? One External Bus Interface (EBI)

– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash? and ECC-enabled NAND Flash

? Memory Controller (MC)

– Embedded Flash Controller

– Memory Protection Unit

– Abort Status and Misalignment Detection

? Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector

– Provides External Reset Signal Shaping and Reset Source Status

? Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL

? Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode

– Three Programmable External Clock Signals

? Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected

? Debug Unit (DBGU)

– Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention

? Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

? Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter

– Provides Reset or Interrupt Signals to the System

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

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