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EP2C20中文資料
EP2C20數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情
Introduction
Following the immensely successful first-generation Cyclone? device family, Altera? Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost.
Features The Cyclone II device family offers the following features:
■ High-density architecture with 4,608 to 68,416 LEs
● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation
■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers
■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore? function
● 133-MHz PCI-X 1.0 specification compatibility
● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
● Programmable bus-hold feature
● Programmable output drive strength feature
● Programmable delays from the pin to the IOE or logic array
● I/O bank grouping for unique VCCIO and/or VREF bank settings
● MultiVolt? I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
● Hot-socketing operation support
● Tri-state with weak pull-up on I/O pins before and during configuration
● Programmable open-drain outputs
● Series on-chip termination support
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EP2C20產(chǎn)品屬性
- 類型
描述
- 型號(hào)
EP2C20
- 制造商
ALTERA
- 制造商全稱
Altera Corporation
- 功能描述
SECTION IV. I/O STANDARDS
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
ALTERA |
23+ |
BGA |
500 |
優(yōu)勢(shì)渠道、優(yōu)勢(shì)價(jià)格 |
|||
ALTERA |
21+ |
QFP240 |
2000 |
全新原裝 鄙視假貨 |
|||
ALTERA |
24+ |
BGA |
2210 |
原裝正品!公司現(xiàn)貨熱賣! |
|||
ALTERA |
2020+ |
FBGA256 |
1620 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫(kù)存 本公司只做原裝 可 |
|||
ALTERA |
17+ |
BGA |
4500 |
進(jìn)口原裝!長(zhǎng)期供應(yīng)!絕對(duì)優(yōu)勢(shì)價(jià)格(誠(chéng)信經(jīng)營(yíng) |
|||
ALTERA |
24+ |
QFP240 |
8000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
|||
ALTERA |
1172 |
原裝正品 |
|||||
ALTERA |
24+ |
QFP |
2500 |
授權(quán)代理直銷,原廠原裝現(xiàn)貨,假一罰十,特價(jià)銷售 |
|||
ALTERA |
21+ |
BGA256 |
1516 |
十年信譽(yù),只做原裝,有掛就有現(xiàn)貨! |
|||
Altera |
23+ |
BGA |
600 |
正規(guī)渠道,只有原裝! |
EP2C20Q240C8N 價(jià)格
參考價(jià)格:¥341.0363
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Datasheet數(shù)據(jù)表PDF頁(yè)碼索引
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Altera Corporation 阿爾特拉公司
Altera Corporation(阿爾特拉公司)是一家知名的可編程邏輯器件制造商。 該公司的主要產(chǎn)品包括現(xiàn)場(chǎng)可編程門陣列(FPGA)、復(fù)雜可編程邏輯器件(CPLD)、嵌入式系統(tǒng)、專用集成電路(ASIC)等,具體如下: - FPGA產(chǎn)品:擁有多個(gè)系列,如Stratix系列(大規(guī)模高端FPGA)、Arria系列(中規(guī)模FPGA)、Cyclone系列(低成本FPGA)等。這些FPGA具有不同的特點(diǎn)和性能,可滿足各種應(yīng)用需求,例如Stratix系列具有較大規(guī)模、高帶寬、高性能等特點(diǎn);Cyclone系列則更側(cè)重于低成本和通用應(yīng)用。不同系列的FPGA產(chǎn)品會(huì)不斷更新迭代,以適應(yīng)市場(chǎng)需求和技術(shù)發(fā)展。 -