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GENERAL DESCRIPTION

The ADN4666 is a quad-channel, CMOS low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption.

The device accepts low voltage (350 mV typical) differential input signals and converts them to a single-ended, 3 V TTL/CMOS logic level.

The ADN4666 also offers active high and active low enable/disable inputs (EN and EN) that control all four receivers. These inputs disable the receivers and switch the outputs to a high impedance state. Consequently, the outputs of one or more ADN4666 devices can be multiplexed together to reduce the quiescent power consumption to 10 mW typical.

FEATURES

±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins

400 Mbps (200 MHz) switching rates

100 ps channel-to-channel skew (typical)

100 ps differential skew (typical)

3.3 ns propagation delay (maximum)

3.3 V power supply

High impedance outputs on power-down

Low power design (10 mW quiescent typical)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (350 mV typical) differential

input signal levels

Supports open, short, and terminated input fail-safe

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range of ?40°C to +85°C

Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers